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MPC8544EBVTALJ 数据表(PDF) 31 Page - Freescale Semiconductor, Inc |
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MPC8544EBVTALJ 数据表(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 120 page  MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 31 Enhanced Three-Speed Ethernet (eTSEC), MII Management clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. A summary of the FIFO AC specifications appears in Table 28 and Table 29. Table 28. FIFO Mode Transmit AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5% Parameter/Condition Symbol Min Typ Max Unit Notes TX_CLK, GTX_CLK clock period tFIT —8.0 — ns — TX_CLK, GTX_CLK duty cycle tFITH 45 50 55 % — TX_CLK, GTX_CLK peak-to-peak jitter tFITJ —— 250 ps — Rise time TX_CLK (20%–80%) tFITR — — 0.75 ns — Fall time TX_CLK (80%–20%) tFITF — — 0.75 ns — GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time tFITDX 0.5 — 3.0 ns 1 Note: 1. Data valid tFITDV to GTX_CLK Min setup time is a function of clock period and max hold time. (Min setup = Cycle time – Max hold). Table 29. FIFO Mode Receive AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5% Parameter/Condition Symbol Min Typ Max Unit Notes RX_CLK clock period tFIR —8.0 — ns — RX_CLK duty cycle tFIRH/tFIRH 45 50 55 % — RX_CLK peak-to-peak jitter tFIRJ —— 250 ps — Rise time RX_CLK (20%–80%) tFIRR — — 0.75 ns — Fall time RX_CLK (80%–20%) tFIRF — — 0.75 ns — RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 — — ns — RX_CLK to RXD[7:0], RX_DV, RX_ER hold time tFIRDX 0.5 — — ns — |
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