MPC8544EBVTALJ datasheet(111/120 Pages) FREESCALE

111 / 120 page

MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

111

System Design Information

Table 73 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,

nominal OVDD, 90°C.

21.8

Configuration Pin Muxing

The MPC8544E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped

with an on-chip gated resistor of approximately 20 k

Ω. This value should permit the 4.7-kΩ resistor to pull

the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and

for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input

receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with

minimal signal quality or delay disruption. The default value for all configuration bits treated this way has

been encoded such that a high voltage level puts the device into the default state and external resistors are

needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up

devices.

21.9

JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 69. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but is provided on all processors built on Power Architecture™ technology.

The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does

not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state

Table 73. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI

DDR DRAM

Symbol

Unit

43 Target

25 Target

20 Target

43 Target

25 Target

20 Target

Note: Nominal supply voltages. See Table 1.

MPC8544EBVTALJ 数据表(PDF) 111 Page - Freescale Semiconductor, Inc

MPC8544EBVTALJ 数据表(HTML) 111 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载