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ST7528 数据表(PDF) 21 Page - Sitronix Technology Co., Ltd. |
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ST7528 数据表(HTML) 21 Page - Sitronix Technology Co., Ltd. |
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21 / 97 page  ST7528 Ver2.3 21/97 2007/1/3 FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The ST7528 can interface with an MPU when CSB is "L". When these pins are set to any other combination, A0, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface ST7528 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table 1. Table 1 Parallel / Serial Interface Mode Type PS2 PS1 PS0 CSB Interface mode L H 6800-series MPU mode Parallel L L H CSB 8080-series MPU mode L L L CSB 3-Line SPI mode L H L CSB 4-Line SPI mode Serial H L L CSB IIC SPI mode Parallel Interface (PS0 = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2. The type of data transfer is determined by signals at A0, E_RD and RW_WR as shown in Table 3. Table 2 Microprocessor Selection for Parallel Interface PS1 CSB A0 E_RD RW_WR DB0 to DB7 MPU bus H CSB A0 E RW DB0 to DB7 6800-series L CSB A0 /RD /WR DB0 to DB7 8080-series Table 3 Parallel Data Transfer Common 6800-series 8080-series A0 E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR) Description H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction) NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, RW_WR as in case of 6800-series mode. |
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