ST7530 datasheet(21/100 Pages) SITRONIX

21 / 100 page

ST7530

Ver 1.8

21/100

2006/9/18

8.2 ACCESS TO DDRAM AND INTERNAL REGISTERS

Since ST7530 access from MPU by pipeline processing via the bus holder attached to the internal that requires only the

cycle time but no waiting time, it can achieves high-speed data transfer.

For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the

DDRAM before the succeeding write cycle start. When MPU reads data from the DDRAM, the first read cycle is dummy

and the data read in the dummy cycle is held by the bus holder, and then it read from the bus holder to the system bus in

the succeeding read cycle. Fig. 8.2.1 illustrates these relations.

D(N)

D(N+1) D(N+2)

D(N+3)

D(N)

D(N+1)

D(N+2)

D(N+3)

N+1

N+2

N+3

MPU signal

/WR

DATA

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

Write

Operation

Dummy

D(N)

D(N+1)

MPU signal

/WR

DATA

Internal signals

/W R

COLUMN ADDRESS

/RD

D(N)

D(N+1)

D(N+2)

D(N)

D(N+1)

D(N+2)

/RD

BUS HOLDER

Read

Operation

Fig 8.2.1

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