ST7575 datasheet(17/51 Pages) SITRONIX

17 / 51 page

ST7575

Ver 1.3

17/51

2007/09/12

Test Pins

Pin Name

Type

Description

No. of Pins

T0~T8

Do NOT use. Reserved for testing.

Must be floating.

T11

Do NOT use. Reserved for testing.

Must be “L”. Connect to VSS1 for pull-low.

T12

Do NOT use. Reserved for testing.

Must be “L”. Connect to VSS1 for pull-low.

Recommend ITO Resistance

Pin Name

ITO Resistance

T[0:8], VRS, VDX2O

Floating

VDD1, VDD2, VSS1, VSS2

< 100Ω

V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VMO

< 300Ω

A0, RWR, ERD, CSB, D[7:0]

< 1KΩ

PS[2:0], OSC

*2, CP, BR, TMX, TMY, T11, T12

< 5KΩ

RESB

< 10KΩ

Note:

If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500Ω.

If using internal clock, OSC is connect to VDD1 and the limitation of ITO resistance will be “No Limitation”.

If using external clock, the ITO resistance of OSC should be kept lower than 300Ω to keep the clock signal quality.

To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal

(add a series resistor or increase ITO resistance). The value is different from modules.

The option setting to be “H” should connect to VDD1.

The option setting to be “L” should connect to VSS1.

ST7575 数据表(PDF) 17 Page - Sitronix Technology Co., Ltd.

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