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ST8016 数据表(PDF) 21 Page - Sitronix Technology Co., Ltd. |
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ST8016 数据表(HTML) 21 Page - Sitronix Technology Co., Ltd. |
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21 / 28 page ![]() ST8016 Ver 2.0 Page 21/28 2008/05/07 12.4 Timing Chart of Common Mode LP EIO2 EIO1 /DISPOFF t WDL t SD t DL tH t SU t WLP tR t WLPH tF FR LP Y1 - Y160 tPD1 tPD3 tPD2 /DISPOFF (Common Mode) (VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+85 °C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Shift clock period tWLP tR, tF 20ns 250 ns Shift clock “H” pulse width tWLPH VDD=5± 0.5V VDD=2.5~4.5V 15 30 ns Data setup time tSU 30 ns Data hold time tH 50 ns Input signal rise time tR 50 ns Input signal fall time tF 50 ns DISPOFF removal time tSD 100 ns DISPOFF “L” pulse width tWDL 1.2 us Output delay time (1) tDL CL=10pF 200 ns Output delay time (2) tPD1,tPD2 CL=10pF 1.2 us Output delay time (3) tPD3 CL=10pF 1.2 us |
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