ST8024

Ver 2.1

Page 28/28

2009/08/19

15

REVISION

REVISION

DESCRIPTION

PAGE

DATE

0.20

Add pad location and gold bump data

0.21

Add BLANK contrast control information

0.24

Add TCP (F4) information

0.25

Remove TCP information to another PDF file

ST8024TCP(F4).PDF

0.26

Gold bump strength=30g, update IC diagram

0.27

Correct wrong word mistake

0.28

Correct parameter name

0.29

Correct DI to FLM

0.30

Change operating temperature from -20°C~85°C to

-25°C~85°C

0.31

Change description of TEST1 pin in PIN DESCRIPTION(TCP)

1.0

Add 1 and 48 Gold Bump size

1.2

Modify TCP package

1.3

Rename V5 to Vss and some pins' description

1.4

Modify PAD sequence

1.5

Add alignment mark

1.6

Add max value for input high voltage

16

2006/12/11

1.7

Add wafer thickness information and roughly TCP drawing

information.

Modify chip size and thickness with scribe line and Spec

arrangement

1-27

2006/12/25

1.8

Modify all the data about absolute max voltage and recommend max

voltage

2,16-19

2007/05/25

1.9

Modify Pad Diagram

23

2008/1/14

2.0

Add application note

27

2008/05/07

2.1

Modify Pad Location

24

2009/0819

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permission from Sitronix.