ST8024S datasheet(8/27 Pages) SITRONIX

8 / 27 page

ST8024S

Ver 0.39

Page 8/27

2008/05/05

"H" dual mode operation is selected.

Refer to section 6.2.2.

DI7

Dual mode data input pin

According to the data shift direction of the data shift register, data can be input starting

from the 121st bit.

When the chip is used in dual mode, DI7 will be pulled down.

When the chip is used in single mode, DI7 won't be pulled down.

Refer to section 6.2.2.

S/C

Segment mode/common mode selection pin

When set to LGND level "L", common mode is set.

DI6-DI0

Not used

Connect DI6-DI0 to LGND or VDD, avoiding floating.

XCK

Not used

XCK is pulled down in common mode, so connect to LGND or open.

Y1 -Y240

LCD drive output pins

Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is

selected and output.

Table of truth values is shown in "TRUTH TABLE" in Functional Operations.

6.2

Functional Operations

6.2.1

Truth table

(Segment Mode)

LATCH DATA

/DISPOFF

LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)

V43

VSS

V12

VSS

(Common Mode)

LATCH DATA

/DISPOFF

LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)

V43

V12

VSS

NOTES:

1. VSS < V43 < V12 < V0

2. L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care

3. "Don't care" should be fixed to "H" or "L", avoiding floating.

There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.

Supply regular voltage which is assigned by specification for each power pin.

ST8024S 数据表(PDF) 8 Page - Sitronix Technology Co., Ltd.

ST8024S 数据表(HTML) 8 Page - Sitronix Technology Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

数据表下载