MCP6401RT-ESLASHSL datasheet(13/28 Pages) MICROCHIP

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DS22229A-page 13

MCP6401/1R/1U

4.0

APPLICATION INFORMATION

The

MCP6401/1R/1U

family

amps

manufactured using Microchip’s state-of-the-art CMOS

process and is specifically designed for low-power,

high precision applications.

4.1

Rail-to-Rail Input

4.1.1

PHASE REVERSAL

The MCP6401/1R/1U op amps are designed to prevent

phase reversal when the input pins exceed the supply

voltages.

Figure 2-30

shows

the

input

voltage

exceeding the supply voltage without any phase

reversal.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltage that go too far above

VDD; their breakdown voltage is high enough to allow

normal operation and low enough to bypass ESD

events within the specified limits.

FIGURE 4-1:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these op amps, the circuit they are in must limit the

voltages and currents at the VIN+ and VIN- pins (see

Absolute Maximum Ratings † at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-2

shows the recommended approach to protecting these

inputs. The internal ESD diodes prevent the input pins

(VIN+ and VIN-) from going too far below ground, and

the resistors R1 and R2 limit the possible current drawn

out of the input pins. Diodes D1 and D2 prevent the

input pins (VIN+ and VIN-) from going too far above VDD.

When implemented as shown, resistors R1 and R2 also

limit the current through D1 and D2.

FIGURE 4-2:

Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of the

resistors R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC currents into the input pins (VIN+ and

VIN-) should be very small. A significant amount of

current can flow out of the inputs when the common

mode voltage (VCM) is below ground (VSS). (See

Figure 2-32).

4.1.3

NORMAL OPERATION

The input stage of the MCP6401/1R/1U op amps uses

two differential input stages in parallel. One operates at

a low common mode input voltage (VCM), while the

other operates at a high VCM. With this topology, the

device operates with a VCM up to 300 mV above VDD

and 300 mV below VSS. (See Figure 2-11). The input

offset voltage is measured at VCM = VSS –0.3V and

VDD + 0.3V to ensure proper operation.

The transition between the input stages occurs when

VCM is near VDD – 1.1V (See Figures 2-3 and 2-4). For

the best distortion performance and gain linearity, with

non-inverting gains, avoid this region of operation.

4.2

Rail-to-Rail Output

The output voltage range of the MCP6401/1R/1U op

amps is VSS + 20 mV (minimum) and VDD – 20 mV

(maximum) when RL =10kΩ is connected to VDD/2

and VDD = 6.0V. Refer to Figures 2-23 and 2-24 for

more information.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN–

VDD

R1 >

VSS – (minimum expected V1)

2mA

R2 >

VSS – (minimum expected V2)

2mA

MCP640x

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