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PCA9536DP 数据表(PDF) 13 Page - NXP Semiconductors |
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PCA9536DP 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 22 page ![]() PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 13 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 11. Test information Rise and fall times refer to VIL and VIH Fig 13. I2C-bus timing diagram SCL SDA tHD;STA tSU;DAT tHD;DAT tf tBUF tSU;STA tLOW tHIGH tVD;ACK 002aab175 tSU;STO protocol START condition (S) bit 7 MSB (A7) bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) 1/fSCL tr tVD;DAT RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 14. Test circuitry for switching times Fig 15. Test circuit Table 11. Test data Test Load Switch CL RL tv(Q) 50 pF 500 Ω 2VDD PULSE GENERATOR VO CL 50 pF RL 500 Ω 002aab880 RT VI VDD DUT VDD open VSS CL 50 pF 500 Ω 002aab881 2VDD open VSS S1 from output under test 500 Ω |
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