PCA9536_5

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 05 — 25 January 2010

6 of 22

NXP Semiconductors

PCA9536

6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output. At reset, the

‘Not used’ bits can be programmed with either logic 0 or logic 1.

6.2 Power-on reset

and the PCA9536 registers and state machine will initialize to their default states.

operating voltage.

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input with a weak pull-up (100 k

Ω typical) to V

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the

state of the Output Port register. Care should be exercised if an external voltage is applied

to an I/O configured as an output because of the low-impedance paths that exist between

Table 7.

Register 3 - Configuration register bit description

Legend: * default value

Bit

Symbol

Access

Value

Description

7

C7

R/W

1*

not used

6C6

R/W

1*

5C5

R/W

1*

4C4

R/W

1*

3

C3

R/W

1*

configures the directions of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input

(default value)

2C2

R/W

1*

1C1

R/W

1*

0C0

R/W

1*