AS1113 datasheet(19/24 Pages) AMSCO

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AS1113

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Constant Current

In LED display applications, the AS1113 provides virtually no current variations from channel-to-channel and from

AS1113-to-AS1113. This is mostly due to 2 factors:

While IOUT

≥ 10mA, the maximum current skew is less than ±3% between channels and less than ±6% between

AS1113 devices.

In the saturation region, the characteristic curve of the output stage is flat (see Figure 5 on page 7). Thus, the out-

put current can be kept constant regardless of the variations of LED forward voltages (VF).

Adjusting Output Current

The AS1113 scales up the reference current (IREF) set by external resistor (REXT) to sink a current (IOUT) at each out-

put port. As shown in Figure 3 on page 7 the output current in the saturation region is extremely flat so that it is possi-

ble to define it as target current (IOUT TARGET). IOUT TARGET can be calculated by:

VREXT = 1.253V

(EQ 1)

IREF = VREXT/REXT (if the other end of REXT is connected to ground)

(EQ 2)

IOUT TARGET = IREF*15 = (1.253V/REXT)*15

(EQ 3)

Where:

REXT is the resistance of the external resistor connected to pin REXT.

VREXT is the voltage on pin REXT.

The magnitude of current (as a function of REXT) is around 50.52mA at 372

Ω and 25.26mA at 744Ω. Figure 3 on

page 7 shows the relationship curve between the IOUT TARGET of each channel and the corresponding external resistor

(REXT).

Package Power Dissipation

The maximum allowable package power dissipation (PD) is determined as:

PD(MAX) = (TJ-TAMB)/RTH(J-A)

(EQ 4)

When 16 output channels are turned on simultaneously, the actual package power dissipation is:

PD(ACT) = (IDD*VDD) + (IOUT*Duty*VDS*16)

(EQ 5)

Therefore, to keep PD(ACT)

≤ PD(MAX), the maximum allowed output current as a function of duty cycle is:

IOUT = {[(TJ-TAMB)/RTH(J-A)]-(IDD*VDD)}/VDS/Duty/16

(EQ 6)

Where:

TJ = 150ºC

Delayed Outputs

The AS1113 has graduated delay circuits between outputs. These delay circuits can be found between OUTNn and

constant current block.

The fixed delay time is 20 ns (typ) where OUTN0 has no delay, OUTN1 has 20ns delay, OUTN2 has 40ns delay ...

OUTN15 has 300ns delay. This delay prevents large inrush currents, which reduce power supply bypass capacitor

requirements when the outputs turn on (see Figure 10 on page 10)

Switching-Noise Reduction

LED drivers are frequently used in switch-mode applications which normally exhibit switching noise due to parasitic

inductance on the PCB.

Load Supply Voltage

Considering the package power dissipation limits (see EQ 4:6), the AS1113 should be operated within the range of

VDS = 0.4 to 1.0V.

For example, if VLED is higher than 5V, VDS may be so high that PD(ACT) > PD(MAX) where VDS = VLED - VF. In this case,

the lowest possible supply voltage or a voltage reducer (VDROP) should be used. The voltage reducer allows

VDS = (VLED -VF) - VDROP.

Note: Resistors or zener diodes can be used as a voltage reducer as shown in Figure 22.

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