www.austriamicrosystems.com

Revision 1.01

13 - 15

AS1153/55

Data Sheet - P a c k age Drawin gs an d Ma rkings

10 Package Drawings and Markings

The AS1155/58 and AS1153/57 are available in a 8-pin SOIC package.

Figure 22. 8-pin SOIC Package Diagram

Note:

1. Lead coplanarity should be 0 to 0.10MM max.

2. Package surface finishing:

Top: Matte (Charmilles #18~30)

All Sides: Matte (Charmilles #18~30)

Bottom: Smooth or Matte (Charmilles #18~30)

3. All dimension excluding Mold Flashes and End Flash from the package body shall not exceed 0.25MM per side (D)

4. Details of PIN #1 identifier are optional, but must be located within the zone indicated.

Table 6. 8-pin SOIC Package Dimensions

SOIC - 8LD

Symbol

MILLIMETERS

Symbol

MILLIMETERS

MIN

MAX

MIN

MAX

A1

0.10

0.25

h

0.25

0.50

B

0.36

0.48

L

0.41

1.27

D

4.80

4.98

A

1.52

1.72

E

3.81

3.99

0º

8º

e

1.27 BSC

ZD

0.53 REF

H

5.80

6.20

A2

1.37

1.57