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Revision 1.03

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AS1526/AS1527

9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN,

produce trailing zeros at DOUT and have no effect on the conversion process.

10. For minimum cycle time, clock out the data with 10.5 clock cycles at full speed using the rising edge of DOUT as

be pulled low to initiate the next conversion.

Figure 25. Serial Interface Standard Cycle Timing Diagram

Figure 26. Serial Interface Minimum Cycle Timing Diagram

Figure 27. Detailed Serial Interface Timing Diagram

CSN

SCLK

DOUT

Conversion

In Progress

Hold

EOC

Track/Hold

Stage

Track

Clock Out Serial Data

Track

Cycle Time

Total = 13.7µs

Trailing

0s

Idle

0.24µs

0µs

7.5µs

Hold

Interface

Idle

B9 B8 B7 B6 B5 B4 B3 B2 B1

B0 S1 S0

0µs

12.5 x 0.476µs = 5.95µs

Sub

Bits

Hold

Track/Hold

Stage

Track

Track

Hold

Total = 12.74µs

Cycle Time

DOUT

B9

B8

B7

B6

B5

B4

B3

B1

B0

CSN

EOC

Clock Out Serial Data

Idle

Interface

Idle

0.24µs

7.5µs

0µs

10.5 x 0.476µs = 5µs

SCLK

B2

Conversion

In Progress

Track/Acquire

CSN

SCLK

DOUT

Internal

Track/Hold

Hold

Track/Acquire

B0

S1

S0