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Revision 1.03

17 - 21

AS1526/AS1527

Figure 33. Microwire Serial Interface Connections

A conversion process begins on the falling edge of CSN (see Figure 34). DOUT goes low, indicating a conversion is in

progress. Wait until DOUT goes high or until the maximum specified conversion time elapses before starting another

conversion. Two consecutive 1-byte reads are required to retrieve the full 10+2 bits from the devices.

Output data transitions occurs on the falling edge of SCLK, and is clocked into the microprocessor on the rising edge of

SCLK. The first byte contains a leading 1, and seven bits of conversion result data. The second byte contains the

remaining three bits of conversion result data, two sub-bits, and three trailing zeros.

Figure 34. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)

QSPI

When interfacing the AS1526/AS1527 to a microprocessor’s QSPI interface (see Figure 35), set QSPI control register

CPOL = CPHA = 0.

Figure 35. QSPI Serial Interface Connections

AS1526/

AS1527

CPU

SI

I/O

SK

6

DOUT

7

CSN

8

SCLK

1st Byte Read

2nd Byte Read

LSB

MSB

EOC

CSN

SCLK

DOUT

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

S1

S0

High-Z

when CSN

is High

AS1526/

AS1527

CPU

SSM

MISO

CSM

SCK

6

DOUT

7

CSN

8

SCLK