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AS1531 数据表(PDF) 17 Page - ams AG |
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AS1531 数据表(HTML) 17 Page - ams AG |
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17 / 29 page ![]() www.austriamicrosystems.com Revision 1.02 17 - 29 AS1530/AS1531 Data Sheet - Deta iled Description Starting a Conversion A conversion is started by clocking a control byte into pin DIN. With CSN low, each rising edge on SCLK clocks a bit from DIN into the internal shift register, starting with the MSB. A conversion will only start when a logic 1 is written to the START bit of the 8-bit control register. Figure 21. Single Conversion Timing Waveforms Figure 22. Continuous 16-Clock Conversion Timing Waveforms RANGE B11 B10 B9 B8 B7 B0 B1 B2 B3 B4 B5 B6 tACQ RB1 RB2 RB3 Single Conversion Acquire Idle Idle 1 4 8 9 12 20 16 24 Start High-Z High-Z High-Z High-Z CSN SCLK DIN SSTRB DOUT SEL2 SEL1 SEL0 MODE PD0 PD1 High-Z CSN DIN SSTRB SCLK B11 B11 B0 B6 B6 B6 B0 ... Conversion Result 0 Conversion Result 1 Control Byte 0 Control Byte 1 Control Byte 2 High-Z B11 112 816 1 12 816 1 12 816 SS S S DOUT Conversion Result 2 |
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