AS1706 datasheet(12/17 Pages) AMSCO

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AS1701, AS1706

Data Sheet - Ap p lica tio n In fo r m a tio n

If the internal power dissipation exceeds the maximum allowed for a given package, power dissipation can be reduced

by increasing the ground plane heat-sinking capabilities and increasing the size of the traces to the device (see Layout

and Grounding Considerations on page 14). Additionally, reducing VDD, increasing load impedance, and decreasing

ambient temperature can reduce device power dissipation.

The integrated thermal-overload protection circuitry limits the total device power dissipation. Note that if the junction

temperature is

≥ +145°C, the integrated thermal-overload protection circuitry will disable the amplifier output stage. If

the junction temperature is reduced by 9ºC, the amplifiers will be re-enabled.

Note:

A pulsing output under continuous thermal overload results as the device heats and cools.

Efficiency

Efficiency of the AS1701/AS1706 is calculated by taking the ratio of the power delivered to the load, to the power con-

sumed from the power supply. Output power is calculated by:

where VPEAK is half the peak-to-peak output voltage. In BTL amplifier configurations, the supply current waveform is a

full-wave rectified sinusoid with the magnitude proportional to the peak output voltage and load.

Calculate the supply current and power drawn from the power supply by:

The efficiency of the AS1701/AS1706 is:

Component Selection

Gain-Setting Resistors

External feedback resistors RF and RIN (see Figure 1 on page 1) set the gain of the device as:

Optimum output offset is achieved when RF = 20k

Ω. Device gain can be varied by changing the value of RIN.

If used in a high-gain configuration (greater than 8V/V), a feedback capacitor may be required to maintain stability (see

Figure 1 on page 1). CF and RF limit the bandwidth of the device, preventing high-frequency oscillations.

Note:

Ensure that the pole created by CF and RF is not within the frequency band of interest.

POUT =

π2RL

(EQ 7)

VPEAK

IDD =

πRL

(EQ 8)

2VPEAK

PIN = VDD

πRL

(EQ 9)

2VPEAK

η =

(EQ 10)

2VDD

RIN

POUT

POUTRL

AVD = 2 x

RIN

(EQ 11)

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