| 数据搜索系统,热门电子元器件搜索 |
|
AS1747 数据表(PDF) 9 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS1747 数据表(HTML) 9 Page - ams AG |
|
9 / 13 page ![]() www.austriamicrosystems.com Revision 1.01 9 - 13 AS1747 Datasheet - Ti m i n g D i a g r a m s 10 Timing Diagrams Figure 15. Switching Time Figure 16. Break-Before-Make Interval Figure 17. Charge Injection VOUT CL RL VN_ VCC VCC COM_ IN_ NO_ OR NC_ GND Logic Input CL includes fixture and stray capacitance VOUT = VN_(RL / (RL + RON)) 50% tr < 5ns tf < 5ns 0V 0V VOUT tON tOFF 0.9 x VOUT 0.9 x VOUT Logic Input Switch Output VCC IN depends on switch configuration; Input polarity determined by sense of switch. VOUT CL RL VN_ VCC VCC COM_ IN_ NO_ GND Logic Input CL includes fixture and stray capacitance 50% 0V VOUT tBBM 0.9 x VOUT Logic Input VCC NC_ VOUT CL VCC VCC COM_ NC_ OR NO_ Logic input waveforms inverted for switches that have the opposite logic sense. GND VIL to VIH RGEN VGEN + IN_ ΔVOUT VOUT Q = ( ΔVOUT)(CL) ON ON OFF OFF OFF OFF IN IN |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |