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AS1925/AS1926

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

9 Application Information

Figure 9. Typical Application Diagram

Fast Transient Immunity

duration versus reset comparator overdrive, for which the devices do not generate a reset pulse. The graph was gen-

transient can have without causing a reset pulse. As the magnitude of the transient goes further below the reset

threshold, the maximum allowable pulse width decreases.

Ensuring a Valid Reset Output Down to 0V

cuit, which means that high-impedance CMOS-logic inputs connected to RESETN can drift to undetermined voltages.

This is not relevant for most applications since most microprocessors and other circuits do not operate with a supply

voltage < 0.55V.

In systems where RESETN must be valid down to 0V, adding a pulldown resistor to RESETN (see Figure 10) causes

any stray leakage currents to flow to ground, holding RESETN low. The value of the pulldown resistor is not critical; a

200k

Ω resistor is large enough not to load RESETN and small enough to pull RESETN to ground.

Note: A 200k

0.75V.

AS1926

External

Reset

CPU

RESETN

I/O

Supply

0.9V

GND

DC/DC

Converter

+3.3V

GND

2

5

1

RESETN

4

MRN

AS1925

GND

2

5

1

RESETN