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AS5030ATST 数据表(PDF) 8 Page - ams AG |
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AS5030ATST 数据表(HTML) 8 Page - ams AG |
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8 / 33 page  AS5030 8-bit Programmable Magnetic Rotary Encoder Rev. 1.8 www.austriamicrosystems.com Page 8 of 33 4.10 Serial 8-bit Output Parameter SYMBOL MIN TYP MAX UNIT NOTE 3-wire interface fCLK 6 MHz Clock frequency tCLK 166.6 ns normal operation Clock frequency fclk,P 250 500 kHz during OTP programming 2-wire interface fCLK 0.1 6 MHz Clock frequency tCLK 166.6 10,000 ns normal operation Clock frequency fclk,P 250 500 kHz during OTP programming Synchronization timeout tTO 16.6 27 34.3 ms Rising edge of CLK to internally generated chip select on pin DX Digital hysteresis1) Hyst 1 bit at change of rotation direction Note: 1) Hysteresis may be temporarily disabled by software: see 5.2.2 4.11 General Data Transmission Timings Parameter Symbol Min Max Unit rising CLK to CS t0 15 - ns chip select to positive edge of CLK t1 15 - ns chip select to drive bus externally t2 - - ns setup time command bit data valid to positive edge of CLK t3 30 ns hold time command bit data valid after positive edge of CLK t4 30 ns float time positive edge of CLK for last command bit to bus float t5 30 CLK/2 ns bus driving time positive edge of CLK for last command bit to bus drive t6 CLK/2 +0 CLK/2 +30 ns setup time data bit data valid to positive edge of CLK t7 CLK/2 +0 CLK/2 +30 ns hold time data bit data valid after positive edge of CLK t8 CLK/2 +0 CLK/2 +30 ns hold time chip select positive edge CLK to negative edge of chip select t9 30 ns bus floating time negative edge of chip select to float bus t10 0 30 ns hold time data bit @ write access data valid to positive edge of CLK t11 50 ns hold time data bit @ write access data valid after positive edge of CLK t12 30 ns bus floating time negative edge of chip select to float bus t13 50 ns Timeout period in 2-wire mode (from rising edge of CLK) tTO 20 24 µs See the Figure 5 for the corresponding timing diagram. |
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