AS5311

Data Sheet

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Revision 1.01

15 - 23

8

Pulse Width Modulation (PWM) Output

The AS5311 provides a pulse width modulated output (PWM), whose duty cycle is proportional to the relative

linear position of the magnet within one pole pair (2.0mm). This cycle repeats after every subsequent pole pair:

4098 −

+

⋅

=

off

on

on

t

t

t

Position

for digital position = 0 – 4094

Exception:

A linear position of 1999.5µm = digital position 4095

The PWM frequency is internally trimmed to an accuracy of

±5% (±10% over full temperature range). This

tolerance can be cancelled by measuring the complete duty cycle as shown above.

Figure 10: PWM Output Signal

Position

1999.5µm

(Pos 4095)

0µm

(Pos 0)

1µs

4098µs

4097µs

9

3.3V / 5V Operation

The AS5311 operates either at 3.3V ±10% or at 5V ±10%. This is made possible by an internal 3.3V Low-

Dropout (LDO) Voltage regulator. The internal supply voltage is always taken from the output of the LDO,

meaning that the internal blocks are always operating at 3.3V.

For 3.3V operation, the LDO must be bypassed by connecting VDD3V3 with VDD5V (see Figure 11).

For 5V operation, the 5V supply is connected to pin VDD5V, while VDD3V3 (LDO output) must be buffered by a

2.2...10µF capacitor, which is supposed to be placed close to the supply pin.

The VDD3V3 output is intended for internal use only It must not be loaded with an external load.

The output voltage of the digital interface I/O’s corresponds to the voltage at pin VDD5V, as the I/O buffers are

supplied from this pin.

A buffer capacitor of 100nF is recommended in both cases close to pin VDD5V. Note that pin VDD3V3 must

always be buffered by a capacitor. It must not be left floating, as this may cause an instable internal 3.3V supply

voltage which may lead to larger than normal jitter of the measured angle.