PIC12F617-ESLASHMS datasheet(73/212 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41302D-page 73

PIC12F609/615/617/12HV609/615

9.8

Comparator Gating Timer1

This feature can be used to time the duration or interval

of analog events. Clearing the T1GSS bit of the

CMCON1 register will enable Timer1 to increment

based on the output of the comparator. This requires

that Timer1 is on and gating is enabled. See

Section 7.0 “Timer1 Module with Gate Control” for

details.

It is recommended to synchronize the comparator with

Timer1 by setting the CMSYNC bit when the

comparator is used as the Timer1 gate source. This

ensures Timer1 does not miss an increment if the

comparator changes during an increment.

9.9

Synchronizing Comparator Output

to Timer1

The comparator output can be synchronized with

Timer1 by setting the CMSYNC bit of the CMCON1

latched on the falling edge of the Timer1 clock source.

If a prescaler is used with Timer1, the comparator

output is latched after the prescaling function. To

prevent a race condition, the comparator output is

latched on the falling edge of the Timer1 clock source

and Timer1 increments on the rising edge of its clock

source. See the Comparator Block Diagram (Figure 9-

2) and the Timer1 Block Diagram (Figure 7-1) for more

information.

CMCON1: COMPARATOR CONTROL REGISTER 1

U-0

R/W-0

U-0

R/W-1

R/W-0

—

T1ACS

CMHYS

—

T1GSS

CMSYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

Unimplemented: Read as ‘0’

bit 4

T1ACS: Timer1 Alternate Clock Select bit

= Timer 1 Clock Source is System Clock (FOSC)

= Timer 1 Clock Source is Instruction Clock (FOSC\4)

bit 3

CMHYS: Comparator Hysteresis Select bit

= Comparator Hysteresis enabled

= Comparator Hysteresis disabled

bit 2

Unimplemented: Read as ‘0’

bit 1

T1GSS: Timer1 Gate Source Select bit(1)

= Timer 1 Gate Source is T1G pin (pin should be configured as digital input)

= Timer 1 Gate Source is comparator output

bit 0

CMSYNC: Comparator Output Synchronization bit(2)

= Output is synchronized with falling edge of Timer1 clock

= Output is asynchronous

Note 1:

Refer to Section 7.6 “Timer1 Gate”.

Refer to Figure 9-2.

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