TS2GDOM40V datasheet(35/52 Pages) TRANSCEND

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Transcend Information Inc.

Ver 1.7

Ultra DMA Sender and Recipient IC Timing Requirements

UDMA Mode 0 (ns) UDMA Mode 1 (ns) UDMA Mode 2 (ns) UDMA Mode 3 (ns) UDMA Mode 4 (ns)

Name

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

tDSIC

14.7

9.7

6.8

4.8

tDHIC

4.8

tDVSIC

72.9

50.9

33.9

22.6

9.5

tDVHIC

9.0

tDSIC

Recipient IC data setup time (from data valid until STROBE edge) (see note 2)

tDHIC

Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2)

tDVSIC

Sender IC data valid setup time (from data valid until STROBE edge) (see note 3)

tDVHIC

Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)

Notes:

(1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.

(2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and

falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured

through 1.5 V).

(3) The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all

signals have the same capacitive load value. Noise that may couple onto the output signals from external

sources has not been included in these values.

Ultra DMA AC Signal Requirements

Name

Comment

Min[V/ns]

Max [V/ns]

Note

SRISE

Rising Edge Slew Rate for any signal

1.25

SFALL

Falling Edge Slew Rate for any signal

1.25

Note:

(1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The

signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point.

All other signals should remain connected through to the recipient. The test point may be located at any point

between the sender’s series termination resistor and one half inch or less of conductor exiting the connector.

If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut

within one half inch of the connector.

The test load and test points should then be soldered directly to the exposed source side connectors. The test

loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the

test point to ground. Slew rates shall be met for both capacitor values.

Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500

MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with

data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output high

level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent

falling edge.

TS2GDOM40V 数据表(PDF) 35 Page - Transcend Information. Inc.

TS2GDOM40V 数据表(HTML) 35 Page - Transcend Information. Inc.

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