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Transcend Information Inc.

Ver 1.2

13

Ultra DMA Data Burst Timing Descriptions

Name

Comment

Notes

Typical sustained average two cycle time

Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE

edge)

Two cycle time allowing for clock variations (from rising edge to next rising edge or from

falling edge to next falling edge of STROBE)

Data setup time at recipient (from data valid until STROBE edge)

2,

Data hold time at recipient (from STROBE edge until data may become invalid)

2,

Data valid setup time at sender (from data valid until STROBE edge)

3

Data valid hold time at sender (from STROBE edge until data may become invalid)

3

CRC word setup time at device

2

CRC word hold time device

2

CRC word valid setup time at host (from CRC valid until -DMACK negation)

3

CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid) 3

Time from STROBE output released-to-driving until the first transition of critical timing.

Time from data output released-to-driving until the first transition of critical timing.

First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

Limited interlock time

1

Interlock time with minimum

1

Unlimited interlock time

1

Maximum time allowed for output drivers to release (from asserted or negated)

Minimum delay time required for output

drivers to assert or negate (from released)

Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and

from DMACK to STOP during data out burst initiation)

Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of

-DMARDY)

Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)

Maximum time before releasing IORDY

Minimum time before driving IORDY

4,

Setup and hold times for -DMACK (before assertion or negation)

Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender

terminates a burst)

Notes:

that has a defined maximum.

(3) Timing for

the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing

measurements are not valid in a normally functioning system.

giving it a known state when released.