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ADP151ACBZ-2.8-R7 数据表(PDF) 13 Page - Analog Devices |
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ADP151ACBZ-2.8-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 24 page ![]() ADP151 Rev. 0 | Page 13 of 24 ENABLE FEATURE The ADP151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 28, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. 3.0 2.5 2.0 1.5 0.5 1.0 0 0 0.5 1.0 1.5 2.0 2.5 ENABLE VOLTAGE Figure 28. ADP151 Typical EN Pin Operation As shown in Figure 28, the EN pin has hysteresis built in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds when the input voltage varies from 2.2 V to 5.5 V. 1200 1000 800 600 200 400 0 2.0 2.5 3.0 3.5 4.5 5.0 4.0 5.5 INPUT VOLTAGE VEN RISE VEN FALL Figure 29. Typical EN Pin Thresholds vs. Input Voltage The ADP151 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 3.3 V option is approximately 160 μs from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 30, the start-up time is dependent on the output voltage setting. 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 450 400 350 300 250 200 150 100 50 TIME (µs) ENABLE 3.3V 2.8V 1.1V Figure 30. Typical Start-Up Behavior ADJUSTABLE OUTPUT VOLTAGE OPERATION The unique architecture of the ADP151 makes an adjustable version difficult to implement in silicon. However, it is possible to create an adjustable regulator at the expense of increasing the quiescent current of the regulator circuit. The ADP151, and similar LDOs, are designed to regulate the output voltage, VOUT, appearing at the VOUT pin with respect to the GND pin. If the GND pin is at a potential other than 0 V (for example, at VOFFSET), the ADP151 output voltage is VOUT + VOFFSET. By taking advantage of this behavior, it is possible to create an adjustable ADP151 circuit that retains most of the desirable characteristics of the ADP151. U1 1 2 3 5 4 C2 C1 VOUT VIN VOUT NC VIN GND EN C3 R2 VOFFSET R1 VOUT = VLDO × (1 + R1/R2) Figure 31. Adjustable LDO Using the ADP151 The circuit shown in Figure 31 is an example of an adjustable LDO using the ADP151. A stable VOFFSET voltage is created by passing a known current through R2. The current through R2 is determined by the voltage across R1. Because the voltage across R1 is set by the voltage between VOUT and GND, the current passing through R2 is fixed, and VOFFSET is stable. To minimize the effect variation of the ADP151 ground current, IGND, with load, it is best to keep R1 as small as possible. It is also best to size the current passing through R2 to at least 20× greater than the maximum expected ground current. To create a 4 V LDO circuit, start with the 3.3 V version of the ADP151 to minimize the value of R2. Because VOUT is 4 V, VOFFSET must be 0.7 V, and the current through R2 must be 7 mA. R1 is, therefore, 3.3 V/7 mA or 471 Ω. A 470 Ω standard value introduces less than 1% error. Capacitor C3 is necessary to stabilize the LDO; a value of 1 μF is adequate. |
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