ADP172

Rev. 0 | Page 12 of 20

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP172 is designed for operation with small, space-saving

ceramic capacitors but functions with most commonly used

capacitors as long as care is taken with the effective series

resistance (ESR) value. The ESR of the output capacitor affects

the stability of the LDO control loop. A minimum of 1 μF

capacitance with an ESR of 1 Ω or less is recommended to

ensure the stability of the ADP172. The transient response to

changes in load current is also affected by output capacitance.

Using a larger value of output capacitance improves the

transient response of the ADP172 to large changes in load

current. Figure 24 and Figure 25 show the transient responses

for output capacitance values of 1 μF and 4.7 μF, respectively.

B

W

M200ns

A CH1

112mA

1

2

T

500.000ns

1mA TO 300mA LOAD STEP,

2.5A/µs

B

W

M200ns

A CH1

108mA

1

2

T

500.000ns

1mA TO 300mA LOAD STEP,

2.5A/µs

Input Bypass Capacitor

Connecting a 1 μF capacitor from VIN to GND reduces the

circuit sensitivity to the printed circuit board (PCB) layout,

especially when long input traces or high source impedance

is encountered. If greater than 1 μF of output capacitance is

required, the input capacitor should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitor can be used with the ADP172,

as long as it meets the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior over temper-

ature and applied voltage. Capacitors must have a dielectric

adequate to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. An X5R or X7R

dielectric with a voltage rating of 6.3 V or 10 V is recommended.

The Y5V and Z5U dielectrics are not recommended due to their

poor temperature and dc bias characteristics.

Figure 26 depicts the capacitance vs. bias voltage characteristics

of a 0402, 1 μF, 10 V X5R capacitor. The variance of a capacitor

is strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or with a higher voltage

rating exhibits less capacitance variance over bias voltage. The

temperature variation of the X5R dielectric is about ±15% over

the −40°C to +85°C temperature range and is not a function of

package or voltage rating.

1.2

1.0

0.8

0.6

0.4

0.2

0

0246

8

10

BIAS VOLTAGE (V)

Figure 26. Capacitance vs. Bias Voltage Characteristics

Use Equation 1 to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

(1)

where:

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.