ADP1871ARMZ-0.3-R7 datasheet(34/44 Pages) AD

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ADP1871ARMZ-0.3-R7 数据表(PDF) 34 Page - Analog Devices

部件名	ADP1871ARMZ-0.3-R7

功能描述	Synchronous Buck Controller with Constant On-Time and Valley Current Mode

PDF	44 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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ADP1871ARMZ-0.3-R7 数据表(HTML) 34 Page - Analog Devices

ADP1871ARMZ-0.3-R7 Datasheet HTML 30Page - Analog Devices

ADP1871ARMZ-0.3-R7 Datasheet HTML 31Page - Analog Devices

ADP1871ARMZ-0.3-R7 Datasheet HTML 32Page - Analog Devices

ADP1871ARMZ-0.3-R7 Datasheet HTML 33Page - Analog Devices

ADP1871ARMZ-0.3-R7 Datasheet HTML 34Page - Analog Devices

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ADP1871ARMZ-0.3-R7 Datasheet HTML 36Page - Analog Devices

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ADP1871ARMZ-0.3-R7 Datasheet HTML 38Page - Analog Devices

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34 / 44 page

ADP1870/ADP1871

Rev. 0 | Page 34 of 44

OUTPUT CAPACITORS

ARE MOUNTED ON THE

RIGHTMOST AREA OF

THE EVB, WRAPPING

BACK AROUND TO THE

MAIN POWER GROUND

PLANE, WHERE IT MEETS

WITH THE NEGATIVE

TERMINALS OF THE

INPUT CAPACITORS

ARE MOUNTED CLOSE

TO DRAIN OF Q1/Q2

AND SOURCE OF Q3/Q4.

BYPASS POWER CAPACITOR (C1)

FOR VREG BIAS DECOUPLING

AND HIGH FREQUENCY

CAPACITOR (C2) AS CLOSE AS

POSSIBLE TO THE IC.

SENSITIVE ANALOG

COMPONENTS

LOCATED FAR

FROM THE NOISY

POWER SECTION.

SEPARATE ANALOG GROUND

PLANE FOR THE ANALOG

COMPONENTS (THAT IS,

COMPENSATION AND

FEEDBACK RESISTORS).

Figure 85. Overall Layout of the ADP1870 High Current Evaluation Board

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