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WM2608CDT 数据表(PDF) 6 Page - Wolfson Microelectronics plc |
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WM2608CDT 数据表(HTML) 6 Page - Wolfson Microelectronics plc |
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6 / 13 page ![]() WM2608 Production Data WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001 6 SERIAL INTERFACE X1 2 34 16 X XD15 D14 D13 t WL D1 D0 X SCLK DIN XD15 * D14 * D13 * D12 * D1 * D0 * X DOUT 2 t WH t SUD t HD No high to low transitions t SUC16-FS t WHFS t SUFSCLK FS ( µC MODE) FS (DSP MODE) t WLFS * DIN data from previous word (delayed by 16 clock cycles) Figure 1 Timing Diagram SYMBOL TEST CONDITIONS MIN TYP MAX UNIT tSUFSCLK Setup time, FS pin low before first falling edge of SCLK 8ns tC16-FS Setup time, 16 th falling clock edge after FS low to rising edge of FS (only used in microcontroller mode) 10 ns tWLOADB Pulse duration, LOADB low 10 ns tWH Pulse duration, SCLK high 16 ns tWL Pulse duration, SCLK low 16 ns tSUD Setup time, data ready before SCLK falling edge 8ns tHD Hold time, data held valid after SCLK falling edge 5ns tWHFS Pulse duration, FS high 10 ns tWLFS Pulse duration, FS low 10 ns ts DAC Output settling time see Dynamic DAC Specifications |
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