WM2623

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 October 2000

8

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial clock rate is:

MHz

t

t

f

WL

WH

SCLK

20

1

min

min

max

=

+

=

Since a data word contains 16 bits, the sample rate is limited to

()

MHz

t

t

f

WL

WH

s

25

.

1

16

1

min

min

max

=

+

=

However, the DAC settling time to 8 bits accuracy limits the response time of the analogue output

for large input step transitions.

SOFTWARE CONFIGURATION OPTIONS

Table 2 shows the composition of a 16 bit data word. D11-D4 contains the 8-bit data word, and

D14-D13 hold the programmable options. Bits D15, D12, and D3 through D0 should be set to

ZERO.

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

SPD PWR

0

New DAC value (8 bits)

0

0

0

0

Table 2 Register Map

PROGRAMMABLE SETTLING TIME

SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode,

where typical settling time to within

±0.5LSB of the final value is 3µs. a ZERO puts the device into

the slow mode, where typical settling time is 9

µs.

PROGRAMMABLE POWER DOWN

The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active,

or fully powered up, a ONE configures the device into power down mode. When the power down

function is released the device reverts to the DAC code set prior to power down.