Production Data

WM9703

WOLFSON MICROELECTRONICS LTD

PD Rev 3.4 January 2001

13

Signals from the PCM DAC channels do not have stereo enhancement applied. It is assumed that

these signals will already have been processed digitally with any required 3D enhancement effect.

Applying the analogue 3D enhancement will corrupt this digital effect. This is equivalent to setting the

POP bit in register 20h. As a result, the readback value of this bit is fixed as 1, and attempts to

change it will be ignored. POP bit is set to one and cannot be re-set.

VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this device support all the recommended sample rates specified in the Intel

Revision 2.1 specification for both audio and modem rates. Default rates are 48ks/s. If alternative

rates are selected, the AC’97 interface continues to run at 48k words per second, but data is

transferred across the link in bursts such that the net sample rate selected is achieved. It is up to the

AC’97 Revision 2.1 compliant controller to ensure that data is supplied to the AC link, and received

from the AC link, at the appropriate rate.

The device supports on demand sampling. That is, when the DAC signal processing circuits need

another sample, a sample request is sent to the controller which must respond with a data sample in

the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will

request a sample from the controller every other frame, for each of the stereo DACs. Note that if an

unsupported rate is written to one of the rate registers, the rate will default to the nearest rate

supported. The register will then respond when interrogated with the supported rate the device has

defaulted to.

ADCs are controlled similarly but with one difference: Normally the left and right channel ADCs

sample at the same rate.

AUDIO

SAMPLE RATE

CONTROL VALUE

D15-D0

MODEM

SAMPLE RATE

CONTROL VALUE

D15-D0

8000

1F40

7200

1C20

11025

2B11

8228.57 (57600/7)

2024

16000

3E80

8400

20D0

22050

5622

9000

2328

44100

AC44

9600

2580

48000

BB80

10285.71 (72000/7)

282D

12000

2EE0

13714.28 (96000/7)

3592

19200

4B00

24000

5DC0

Table 3 Variable Sample Rates Supported

The following table shows which registers control which DAC rates, versus Mode and ID selected

CODEC ID

FRONT DAC RATE REGISTER

ADC RATE REG

00 and 01

2Ch

10

2Eh

11

2Ch (centre) and 30h (LFE)

32h

Table 4 Variable Rate Register Location Versus ID