www.SiliconStandard.com

8 of 14

SS6341

+

+

+

+

+

+

+

+

+

+

POR

-

+

3.6V

Q

R

S

Q

R

S

-

+

0.2V

5V

SD

POR

2.6V

COUNT 3

VIN2

VCC

1.3V

200uA

9.5V

FB2

GATE2

OCSET

COMP1

R

R

Q

S

1.3V

FB3

OSCILLATOR

GATE CONTROL

SS

SLOW DISCHARGE

FAST DISCHARGE

20uA

10uA

ERROR AMP

PWM COMP

200KHz

70K

4V

SS

INHIBIT

LUV

OC1

LUV

OC1

PHASE

UGATE

VCC

PGND

LGATE

VCC

0.3V

1.26V

FB1

GATE3

GND

The SS6341 is designed for applications with multiple

voltage demand. This IC has one PWM controller and two

linear controllers. The PWM controller is designed to

converter configuration. The regulated voltage level is

decided by a resistor divider network.

The

Power-On

Reset

(POR)

function

continually

monitors the +12V input supply voltage at VCC pin, the

5V input voltage at OCSET pin, and the 3.3V input at

VIN2 pin. The POR function initiates soft-start operation

after all three input supply voltage exceed their POR

thresholds.

Soft-Start

The POR function initiates the soft-start sequence.

Initially, the voltage on the SS pin rapidly increases to

approximate 1V. Then an internal 10µA current source

As the SS pin voltage slews from 1V to 4V, the PWM

error amplifier reference input (non-inverting terminal)

and output (COMP1 pin) are clamped to a level

proportional to the SS pin voltage. As the SS pin voltage

slews from 1V to 4V, the output clamp generates PHASE

pulses of increasing width that charge the output

capacitors. Additionally both linear regulators’ reference

inputs are clamped to a voltage proportional to the SS pin

voltage. This method provides a controlled smooth rise in

output voltage.

Fig. 2 shows the soft-start sequence for a typical

application. The internal oscillator’s triangular waveform

is compared to the clamped error amplifier output voltage.

As the SS pin voltage increases, the pulse width on the

PHASE pin increases. The period of increasing pulse

Rev.2.01 6/26/2003