X24C01

5

WRITE OPERATIONS

Byte Write

To initiate a write operation, the master sends a start

condition followed by a seven bit word address and a write

bit. The X24C01 responds with an acknowledge, then

waits for eight bits of data and then responds with an

acknowledge. The master then terminates the transfer by

generating a stop condition, at which time the X24C01

begins the internal write cycle to the nonvolatile memory.

While the internal write cycle is in progress, the X24C01

inputs are disabled, and the device will not respond to any

requests from the master. Refer to Figure 4 for the

address, acknowledge and data transfer sequence.

Page Write

The most significant five bits of the word address define

the page address. The X24C01 is capable of a four byte

page write operation. It is initiated in the same manner as

the byte write operation, but instead of terminating the

transfer of data after the first data byte, the master can

transmit up to three more bytes. After the receipt of each

data byte, the X24C01 will respond with an acknowledge.

After the receipt of each data byte, the two low order

address bits are internally incremented by one. The high

order five bits of the address remain constant. If the

master should transmit more than four data bytes prior

to generating the stop condition, the address counter will

“roll over” and the previously transmitted data will be

overwritten. As with the byte write operation, all inputs

are disabled until completion of the internal write cycle.

Refer to Figure 5 for the address, acknowledge and data

transfer sequence.

Figure 4. Byte Write

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

X24C01

S

T

A

R

T

WORD

ADDRESS (n)

S

T

O

P

P

A

C

K

DATA n

R

/

W

L

S

B

S

M

S

B

A

C

K

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Figure 5. Page Write

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

X24C01

S

T

A

R

T

S

S

T

O

P

P

A

C

K

A

C

K

A

C

K

M

S

B

WORD

ADDRESS (n)

DATA n

DATA n+1

DATA n+3

A

C

K

R

/

W

L

S

B

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