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SS6782G

9/21/2005 Rev.3.01

TIMING DIAGRAM

0V

SAFETY TIMER TEST

∆T/∆t TEST

PEAK TIMER TEST

Power

ON

Init.

GND

GND

GND

Floating

VCC

Floating

Floating

Floating

4V

(-0.15%)

(-0.15%)

(-2.5%)

4V

ON

OFF

4V

2mV

Step/100mS

2mV

Step/100mS

2V

1.993V

(-0.35%)

2V

2V

ON

1.96V

2V

4V

2V

1.9V

1.997V

1.997V

1.997V

1.5V

(-2.15%)

1.85V

5V

1.12V

ON

ON

OFF

3.2KHz

ON

OFF

ON

OFF

OFF

OFF

OFF

ON

VCC, SEL3, MODE=5V, (DSW FREQ.=820KHz, 25 TIMES of 32.8K)

-

∆V DISABLE TEST

-

∆V TEST

1.32

9

0.4

8

0.12

4

0.74

0.12

2

0.02

10

0.32

5

0.32

0.97

0.32

0.26

3

0.24

0.1

0.5

7

0.12

6

5.89

5.99

6.01

4.57

4.17

3.93

3.43

2.46

2.14

1.26

12.02

1.17

1.38

0.26

0.14

0.14

1

Floating

GND

Floating

Floating

OFF

ON

<2.1V

<2.1V

2V

2V

0.4

16

Delay 0.3

14

0.74

0.12

12

0.26

13

0.24

0.5

15

8.91

8.51

8.27

7.77

7.47

7.21

(A):ICOA

(B):ICOB

(A):ABV

(B):BBV

ADJ

(A):LEA2

(B):LEB2

(A):LEA1

(B):LEB1

(A):ATS

(B):BTS

TIME (A)

(SEC.)

STAGE

SEL1

SEL2

TIME (B)

(SEC.)

STAGE

0

6.11

6.37

6.25

0.14

11

2V

0.1

6.01

3V

0.1

Fig. 17 Timing Diagram of SS6782G in Test Mode