ADA4320-1ACPZ-R7 datasheet(5/16 Pages) AD

部件名	ADA4320-1ACPZ-R7

功能描述	High Power, Low Distortion Upstream

PDF	16 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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5 / 16 page

ADA4320-1

Rev. 0 | Page 5 of 16

TIMING REQUIREMENTS

Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

Clock Pulse Width (tWH)

Clock Period (tC)

Setup Time SDATA vs. Clock (tDS)

Setup Time DATEN vs. Clock (tES)

Hold Time SDATA vs. Clock (tDH)

Hold Time DATEN vs. Clock (tEH)

Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock

VALID DATA-WORD G1

MSB...LSB

VALID DATA-WORD G2

SDATA

CLK

TXEN

ANALOG

OUTPUT

DATEN

tDS

tES

tEH

8 CLOCK CYCLES

GAIN TRANSFER (G1)

GAIN TRANSFER (G2)

tWH

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

SDATA MSB

MSB – 1

MSB – 2

CLK

VALID DATA BIT

tDS

tDH

Figure 3. SDATA Timing

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