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ADP195ACBZ-R7 数据表(PDF) 9 Page - Analog Devices |
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ADP195ACBZ-R7 数据表(HTML) 9 Page - Analog Devices |
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9 / 12 page ![]() ADP195 Rev. 0 | Page 9 of 12 THEORY OF OPERATION GND EN VIN VOUT ADP195 LEVEL SHIFT AND SLEW RATE CONTROL REVERSE POLARITY PROTECTION Figure 17. Functional Block Diagram The ADP195 is a high-side PMOS load switch. It is designed for supply operation between 1.1 V to 3.6 V. The PMOS load switch is designed for low on resistance, 65 mΩ at VIN = 1.8 V and supports greater than 1 A of continuous current. It is a low quiescent current device with a nominal 4 MΩ pull-down resistor on its enable pin (EN). The packaging is a space-saving 1.0 mm × 1.0 mm, 4-ball WLCSP. |
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