74ALVC32D datasheet(7/13 Pages) NXP

7 / 13 page

74ALVC32_2

Product data sheet

Rev. 02 — 10 December 2007

7 of 13

NXP Semiconductors

74ALVC32

Quad 2-input OR gate

Test data is given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 7.

Test circuitry for switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aae331

VEXT

VCC

DUT

Table 9.

Test data

Supply voltage VCC

Input

Load

VEXT

tr, tf

tPLH, tPHL

tPLZ, tPZL

tPHZ, tPZH

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 k

Ω

open

× V

GND

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500

Ω

open

× V

GND

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

6 V

GND

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

6 V

GND

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