74LVC2G02_7

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 07 — 6 June 2008

2 of 16

NXP Semiconductors

74LVC2G02

Dual 2-input NOR gate

3.

Ordering information

4.

Marking

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74LVC2G02DP

−40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

74LVC2G02DC

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74LVC2G02GT

−40 °C to +125 °C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

× 1.95 × 0.5 mm

SOT833-1

74LVC2G02GD

−40 °C to +125 °C

XSON8U

plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3

× 2 × 0.5 mm

SOT996-2

74LVC2G02GM

−40 °C to +125 °C

XQFN8U

plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6

× 1.6 × 0.5 mm

SOT902-1

Table 2.

Marking codes

Type number

Marking code

74LVC2G02DP

V02

74LVC2G02DC

V02

74LVC2G02GT

V02

74LVC2G02GD

V02

74LVC2G02GM

V02

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

001aah780

1A

1B

1Y

2A

2B

2Y

001aah781

1

1

mna105

B

A

Y