CS5529-ASZ datasheet(25/31 Pages) CIRRUS

25 / 31 page

CS5529

DS246F5

Getting Started

The CS5529 has many features. From a software

programmer’s perspective, what should be done

first? To begin, a 32.768 kHz crystal takes approx-

imately 500 ms to start-up. To accommodate for

this, it is recommended that a software delay of ap-

proximately 500 ms to 1 second precede the pro-

cessor’s ADC initialization code before any

registers are accessed in the ADC. This delay time

is dependent on the start-up delay of the clock

source. If a CMOS clock source with no start-up

delay is being used to drive the ADC, then this de-

lay is not necessary.

The converters include an on-chip power on reset

circuit to automatically reset the ADCs shortly af-

ter power up. When power to the CS5529 is ap-

plied, the chip is held in a reset condition until the

32.768 kHz oscillator has started and a counter-

timer elapses. The counter-timer counts 1002 oscil-

lator clock cycles to make sure the oscillator is ful-

ly stable. During this time-out period the serial port

logic is reset and the RV (Reset Valid) bit in the

configuration register is set to indicate that a valid

reset occurred. In normal start-up conditions, this

power-on-reset circuit should reset the chip when

power is applied. If your application may experi-

ence abnormal power start-up conditions, the fol-

lowing

sequence

instructions

should

performed to guarantee the converter begins proper

operation:

1) After power is applied, initialize the serial port

using the serial port synchronization sequence.

2) Write a ‘1’ to the reset bit (RS) of the configu-

ration register to reset the converter.

3) Read the configuration register to determine if

the reset valid bit (RV) is set to ‘1’. If the RV

bit is not set, the configuration register should

be read again.

4) When the RV bit has been set to ‘1’, reset the

RS bit back to ‘0’ by writing to 0x000000 to the

configuration register. Note that while the RS

bit is set to ‘1’ all other register bits in the ADC

will be reset to their default state, and the RS bit

must be set to ‘0’ for normal operation of the

converters.

Once the RS bit has been set to ‘0’, the ADC is

placed in the command state were it waits for a val-

id command to execute. The next step is to load the

configuration register. If you need to do a factory

calibration, perform offset and gain calibration

steps. Then off-load the offset and gain register

contents into EEPROM. These registers can then

be initialized to these conditions when the instru-

ment is used in normal operation. Once calibration

is ready, input the command to start conversions in

either single or continuous conversion mode. Mon-

itor the SDO pin for a flag that the data is ready and

read conversion data.

PCB Layout

The CS5529 should be placed entirely over an ana-

log ground plane with the DGND pin of the device

connected to the analog ground plane. If the design

splits the ground plane, place the analog-digital

plane split immediately adjacent to the digital por-

tion of the chip.

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