CS8421 datasheet(19/36 Pages) CIRRUS

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DS641F4

CS8421

MS_SEL pin

Input M/S

Output M/S

1.0 kΩ ± 1% to GND

Slave

1.96 kΩ ± 1% to GND

Slave

Master (

128 x Fso)

4.02 kΩ ± 1% to GND

Slave

Master (

256 x Fso)

8.06 kΩ ± 1% to GND

Slave

Master (

384 x Fso)

16.2 kΩ ± 1% to GND

Slave

Master (

512 x Fso)

1.0 kΩ ±1% to VL

Master (

128 x Fsi)

Slave

1.96 kΩ ± 1% to VL

Master (

256 x Fsi)

Slave

4.02 kΩ ± 1% to VL

Master (

384 x Fsi)

Slave

8.06 kΩ ± 1% to VL

Master (

512 x Fsi)

Slave

Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL)

SAIF pin

Input Port Configuration

1.0 kΩ ± 1% to GND

I²S up to 32-bit data

1.96 kΩ ± 1% to GND

Left-Justified up to 32-bit data

4.02 kΩ ± 1% to GND

Right-Justified 16-bit data

1.0 kΩ ± 1% to VL

Right-Justified 20-bit data

1.96 kΩ ± 1% to VL

Right-Justified 24-bit data

4.02 kΩ ± 1% to VL

Right-Justified 32-bit data

Table 2. Serial Audio Input Port Start-Up Options (SAIF)

SAOF pin

Output Port Configuration

1.0 kΩ ± 1% to GND

I²S 16-bit data

1.96 kΩ ± 1% to GND

I²S 20-bit data

4.02 kΩ ± 1% to GND

I²S 24-bit data

8.06 kΩ ± 1% to GND

I²S 32-bit data

16.2 kΩ ± 1% to GND

Left-Justified 16-bit data

32.4 kΩ ± 1% to GND

Left-Justified 20-bit data

63.4 kΩ ± 1% to GND

Left-Justified 24-bit data

127.0 kΩ ± 1% to GND

Left-Justified 32-bit data

1.0 kΩ ± 1% to VL

Right-Justified 16-bit data

1.96 kΩ ± 1% to VL

Right-Justified 20-bit data

4.02 kΩ ± 1% to VL

Right-Justified 24-bit data

8.06 kΩ ± 1% to VL

Right-Justified 32-bit data

16.2 kΩ ± 1% to VL

TDM Mode 16-bit data

32.4 kΩ ± 1% to VL

TDM Mode 20-bit data

63.4 kΩ ± 1% to VL

TDM Mode 24-bit data

127.0 kΩ ± 1% to VL

TDM Mode 32-bit data

Table 3. Serial Audio Output Port Start-Up Options (SAOF)

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