GTL2010_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 3 March 2008

3 of 20

NXP Semiconductors

GTL2010

10-bit bidirectional low voltage translator

6.

Pinning information

6.1 Pinning

6.2 Pin description

[1]

HVQFN24 package die supply ground is connected to both GND pin and exposed center pad. GND pin

must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board and for proper heat conduction through the board, thermal vias need to be

incorporated in the printed-circuit board in the thermal pad region.

Fig 2.

Pin configuration for TSSOP24

Fig 3.

Pin configuration for HVQFN24

GTL2010PW

GND

GREF

SREF

DREF

S1

D1

S2

D2

S3

D3

S4

D4

S5

D5

S6

D6

S7

D7

S8

D8

S9

D9

S10

D10

002aac057

1

2

3

4

5

6

7

8

9

10

11

12

14

13

16

15

18

17

20

19

22

21

24

23

002aac058

GTL2010BS

Transparent top view

D7

S6

S7

D6

S5

D5

S4

D4

S3

D3

S2

D2

terminal 1

index area

6

13

5

14

4

15

3

16

2

17

1

18

Table 3.

Pin description

Symbol

Pin

Description

TSSOP24

HVQFN24

GND

1

22[1]

ground (0 V)

SREF

2

23

source of reference transistor

S1 to S10

3, 4, 5, 6, 7, 8, 9,

10, 11, 12

24, 1, 2, 3, 4, 5, 6,

7, 8, 9

Port S1 to Port S10

D1 to D10

22, 21, 20, 19, 18,

17, 16, 15, 14, 13

19, 18, 17, 16, 15,

14, 13, 12, 11, 10

Port D1 to Port D10

DREF

23

20

drain of reference transistor

GREF

24

21

gate of reference transistor