LPC2101_02_03_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 2 June 2009

18 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.17.3 Reset and wake-up timer

Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST

pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by

any source starts the wake-up timer (see wake-up timer description below), causing the

internal chip reset to remain asserted until the external reset is de-asserted, the oscillator

is running, a fixed number of clocks have passed, and the on-chip flash controller has

completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined reset values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down and Deep power-down mode, any wake-up of the processor from

the Power-down modes makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.