LPC2104FBD48SLASH00 datasheet(2/41 Pages) NXP

2 / 41 page

LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

2 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or

full chip erase takes 400 ms.

I Vectored Interrupt Controller with conﬁgurable priorities and vector addresses.

I EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service

routines can continue to execute whilst the foreground task is debugged with the

on-chip RealMonitor software.

I Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of

instruction execution.

I Multiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s), and

SPI.

I Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time

Clock and Watchdog.

I Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 mm × 7 mm)

package.

I 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop with settling time of 100

µs.

I The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz.

I Two low power modes, Idle and Power-down.

I Processor wake-up from Power-down mode via external interrupt.

I Individual enable/disable of peripheral functions for power optimization.

I Dual power supply:

N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 8.3 %).

N I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2104BBD48

LQFP48