S9S08DN60F1CLC datasheet(73/356 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

5.8.3

System Background Debug Force Reset Register (SBDFR)

This high page register contains a single write-only control bit. A serial background command such as

WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are

ignored. Reads always return 0x00.

Figure 5-4. System Background Debug Force Reset Register (SBDFR)

LOC

Loss of Clock — Reset was caused by a loss of external clock.

0 Reset not caused by loss of external clock

1 Reset caused by loss of external clock

LVD

Low-Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will

occur. This bit is also set by POR.

0 Reset not caused by LVD trip or POR.

1 Reset caused by LVD trip or POR.

76543210

00000000

BDFR1

1 BDFR is writable only through serial background debug commands, not from user programs.

Reset:

00000000

= Unimplemented or Reserved

Table 5-4. SBDFR Register Field Descriptions

Field

Description

BDFR

Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow

an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot

be written from a user program.

Table 5-3. SRS Register Field Descriptions

Field

Description

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