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PCA9541APW/01 数据表(PDF) 8 Page - NXP Semiconductors |
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PCA9541APW/01 数据表(HTML) 8 Page - NXP Semiconductors |
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8 / 41 page ![]() PCA9541A_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 16 July 2009 8 of 41 NXP Semiconductors PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset • During a write operation, the PCA9541A will acknowledge bytes sent to the IE and CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since it is a read-only register. The 2 LSBs of the Command Code do not roll over to 00b but stay at 10b. Only the 2 least significant bits are affected by the AI flag. Unused bits must be programmed with zeros. Any command code (write operation) different from ‘000AI 0000’, ‘000AI 0001’, and ‘000AI 0010’ will not be acknowledged. At power-up, this register defaults to all zeros. Each system master controls its own set of registers, however they can also read specific bits from the other system master. 8.3 Interrupt Enable and Control registers description When a master seeks control of the bus by connecting its I2C-bus channel to the PCA9541A downstream channel, it has to write to the CONTROL register (Reg#01). Bits MYBUS and BUSON allow the master to take control of the bus. The MYBUS and the NMYBUS bits determine which master has control of the bus. Table 9 explains which master gets control of the bus and how. There is no arbitration. Any master can take control of the bus when it wants regardless of whether the other master is using it or not. The BUSON and the NBUSON bits determine whether the upstream bus is connected or disconnected to/from the downstream bus. Table 10 explains when the upstream bus is connected or disconnected. Internally, the state machine does the following: • If the combination of the BUSON and the NBUSON bits causes the upstream to be disconnected from the downstream bus, then that is done. So in this case, the values of the MYBUS and the NMYBUS do not matter. Table 4. Command Code register B1 B0 Register name Type Register function 0 0 IE R/W interrupt enable 0 1 CONTROL R/W control switch 1 0 ISTAT R only interrupt status 1 1 not allowed Fig 7. Internal register map 002aae660 IE 0 CONTROL 0 ISTAT 0 IE 1 CONTROL 1 ISTAT 1 PCA9541A REG#00 REG#01 REG#10 IE CONTROL ISTAT MASTER 0 SCL_MST0 SDA_MST0 REG#00 REG#01 REG#10 IE CONTROL ISTAT MASTER 1 SCL_MST1 SDA_MST1 |
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