PCA9632DP2 datasheet(13/38 Pages) NXP

13 / 38 page

PCA9632_3

Product data sheet

Rev. 03 — 15 July 2008

13 of 38

NXP Semiconductors

PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.3.4 Group duty cycle control, GRPPWM

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz ﬁxed frequency

signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM

is then used as a global brightness control allowing the LED outputs to be dimmed with

the same value. The value in GRPFREQ is then a ‘don’t care’.

In the group dimming mode (DMBLNK = 0) global brightness for the 4 outputs is

controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h

(93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the

GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused.

(4)

E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %.

When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers deﬁne a

global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to

10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

In this mode, when GRPFREQ is programmed to provide a blinking with frequency

programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle

resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused.

(5)

E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.

When GRPFREQ is programmed to provide a blinking with frequency programmable from

6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle

resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are

used.

(6)

E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

Table 9.

GRPPWM - Group duty cycle control register (address 06h) bit description

Legend: * default value.

Address

Bit

Symbol

Access

Value

Description

06h

GRPPWM

7:0

GDC[7:0]

R/W

1111 1111

GRPPWM register

duty cycle

GDC 7:4

[],0000

256

-----------------------------------------

duty cycle

GDC 7:2

[],00

256

-----------------------------------

duty cycle

GDC 7:0

[]

256

---------------------------

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