PCF8563_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 21 February 2008

13 of 32

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1]

registers marked ‘x’ are undefined at power-up and unchanged by subsequent resets.

8.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 9).

8.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P); see Figure 10.

05h

days

xxxxxxxx

06h

weekdays

x

x

x

x

x

x

x

x

07h

century_months

x

x

x

x

x

x

x

x

08h

years

x

x

x

x

x

x

x

x

09h

minute_alarm

1

x

x

x

x

x

x

x

0Ah

hour_alarm

1

x

x

x

x

x

x

x

0Bh

day_alarm

1

x

x

x

x

x

x

x

0Ch

weekday_alarm

1

x

x

x

x

x

x

x

0Dh

CLKOUT_control

1

x

x

x

x

x

0

0

0Eh

timer_control

0

x

x

x

x

x

1

1

0Fh

timer

x

x

x

x

x

x

x

x

Table 25.

Address

Register name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fig 9.

Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL