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PCF8564A 数据表(PDF) 20 Page - NXP Semiconductors

部件名 PCF8564A
功能描述  Real time clock and calendar
PDF  44 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8564A 数据表(HTML) 20 Page - NXP Semiconductors

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PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
20 of 44
NXP Semiconductors
PCF8564A
Real time clock and calendar
[1]
Registers marked ‘x’ are undefined at power-on and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a circuit has been implemented to
disable the POR and speed up functional test of the module. The setting of this mode
requires that the I2C signals on the pins SDA and SCL are toggled as illustrated in
Figure 11. All timings shown are required minimums.
Once the override mode has been entered, the chip immediately stops, being reset, and
normal operation may begin, i.e., entry into the EXT_CLK test mode via I2C access. The
override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1
before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal
operation has no effect, except to prevent entry into the POR override mode.
Table 27.
Register reset values[1]
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_1
0
0
0
0
1
0
0
0
01h
Control_2
0
0
0
0
0
0
0
0
02h
Seconds
1
x
x
x
x
x
x
x
03h
Minutes
x
x
x
x
x
x
x
x
04h
Hours
x
x
x
x
x
x
x
x
05h
Days
xxxxxxxx
06h
Weekdays
x
x
x
x
x
x
x
x
07h
Months
x
x
x
x
x
x
x
x
08h
Years
x
x
x
x
x
x
x
x
09h
Minute_alarm
1
x
x
x
x
x
x
x
0Ah
Hour_alarm
1
x
x
x
x
x
x
x
0Bh
Day_alarm
1
x
x
x
x
x
x
x
0Ch
Weekday_alarm
1
x
x
x
x
x
x
x
0Dh
CLKOUT_ctrl
1
x
x
x
x
x
0
0
0Eh
Timer_ctrl
0
x
x
x
x
x
1
1
0Fh
Timer
x
x
x
x
x
x
x
x
Allow 500 ns between the edges of either signal.
Fig 11. POR override sequence
mgm664
SCL
500 ns
2000 ns
SDA
8 ms
override active
power up



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