SC16C751B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 10 October 2008

9 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

6.6 Special software initialization sequence

Upon reset, the SC16C751B will not be able to receive. A special software initialization

sequence must be sent to the device to enable its receiver clock.

The following software sequence can be added to the UART initialization routine, and this

must be done before other registers are initialized.

WRITE LCR 00

WRITE MSR AA

WRITE MSR 55

WRITE MSR CC

WRITE MSR 33

WRITE MSR A5

WRITE MSR C3

WRITE MSR 5C

WRITE MSR 3A

WRITE LSR 20

6.7 Sleep mode

The SC16C751B is designed to operate with low power consumption. A special Sleep

mode is included to further reduce power consumption (the internal oscillator driver is

disabled) when the chip is not being used. With IER[4] enabled (set to a logic 1), the

SC16C751B enters the Sleep mode, but resumes normal operation when a start bit is

detected, a change of state of RX, CTS, or a transmit data is provided by the user. If the

Sleep mode is enabled and the SC16C751B is awakened by one of the conditions

described above, it will return to the Sleep mode automatically after the last character is

transmitted or read by the user. In any case, the Sleep mode will not be entered while an

interrupt(s) is pending. The SC16C751B will stay in the Sleep mode of operation until it is

disabled by setting IER[4] to a logic 0.

6.8 Low power mode

In Low power mode the oscillator is still running and only the clock to the UART core is

⁄

the same conditions as in Sleep mode.

6.9 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconfigured for loopback internally.

MCR[3:0] register bits are used for controlling loopback diagnostic testing. The transmitter

output (TX) and the receiver input (RX) are disconnected from their associated interface

pins, and instead are connected together internally (see Figure 4). The CTS is

disconnected from its normal modem control input pins, and instead is connected

internally to RTS. Loopback test data is entered into the Transmit Holding Register via the

user data bus interface, D0 to D7. The transmit UART serializes the data and passes the

serial data to the receive UART via the internal loopback connection. The receive UART

converts the serial data back into parallel data that is then made available at the user data

interface D0 to D7. The user optionally compares the received data to the initial

transmitted data for verifying error-free operation of the UART TX/RX circuits.