DS41393A-Page 4

© 2009 Microchip Technology, Inc.

7

FUNCTIONAL DESCRIPTION

7.1

Main Schematic

A main application schematic is shown below for the SOIC/SSOP package pinout. See the Pin Diagram section

for the QFN package pinout.

Figure 3 : Main Schematic (SOIC, SSOP package pin out)

7.2

Bill of Materials

Modifying, removing, or adding components may adversely affect touch performance.

Specific manufacturers and part numbers are provided only as a guide. Equivalents can be used.

Label

Qty

Value

Description

Manufacturer

Part Number

C1

1

10 uF

Capacitor – Ceramic, 10uF, 20%, 6.3V, X7R, 0603

AVX

06036D106MAT2A

C2

1

0.1 uF

Capacitor – Ceramic, 0.1uF, 10%, 16V, X7R, 0603

AVX

0603YC104KAT2A

C3, C4, C5

1

2-3

0.01 uF

Capacitor – Ceramic, 0.01uF, 10%, 50V, X7R, 0603

AVX

06035C103KAT2A

D1-D8

2

4-8

130 W

Diode – Bi-dir., 130W, ESD Protection, SOD323

NXP

PESD5V0S1BA

R1

1

20K ohm

Resistor - 20K ohm, 1/10W, 5%, 0603

Yageo America

RC0603JR-0720KL

U1

1

Na

Touch controller IC

Microchip

AR1010 or AR1020

Table 3 : Bill of Materials

Note 1: C5 is only needed for 5-wire applications.

Note 2: D1-D8 are for ESD protection.



4-wire touch screen, use D1-D4



5-wire touch screen, use D1-D5



8-wire touch screen, use D1-D8

The capacitance of alternate ESD diodes may adversely affect touch performance. A lower

capacitance is better. The PESD5V0S1BA parts shown in the reference design have a typical

capacitance of 35pF. Test to ensure that selected ESD protection does not degrade touch

performance.

ESD protection is shown in the reference design, but acceptable protection is dependent on your

specific application. Ensure your ESD solution meets your design requirements.