PIC24F04KA201T-ISLASHST datasheet(97/224 Pages) MICROCHIP

97 / 224 page

Preliminary

DS39937B-page 95

PIC24F04KA201 FAMILY

DSCON: DEEP SLEEP CONTROL REGISTER(1)

R/W-0

U-0

DSEN

—

bit 15

bit 8

U-0

R/W-0

R/C-0, HS

—

DSBOR(2)

RELEASE

bit 7

bit 0

Legend:

C = Clearable bit

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

DSEN:

Deep Sleep Enable bit

= Enters Deep Sleep on execution of PWRSAV #0

= Enters normal Sleep on execution of PWRSAV #0

bit 14-2

Unimplemented:

Read as ‘0’

bit 1

DSBOR:

Deep Sleep BOR Event bit(2)

= The DSBOR was active and a BOR event was detected during Deep Sleep

= The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep

bit 0

RELEASE:

I/O Pin State Release bit

= Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry

= Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and

LAT bits to control their states

Note 1:

All register bits are reset only in the case of a POR event outside of Deep Sleep mode.

Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this

re-arms POR.

PIC24F04KA201T-I/ST 数据表(PDF) 97 Page - Microchip Technology

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